Rapidus 2-nanometer chips to be priced in line with TSMC, president says
Rapidus will price its 2-nanometer chips near TSMC levels, targeting wafer costs around ¥3–3.5 million while outlining a roadmap toward 1.4nm and 1nm development.
Rapidus disclosed plans to set pricing for its 2-nanometer chips roughly on par with Taiwan Semiconductor Manufacturing Co. (TSMC) at an event in Karuizawa, Nagano Prefecture. The announcement, made by Rapidus President Atsuyoshi Koike, indicates wafer prices will be benchmarked against TSMC’s established levels. The company said it aims to remain cost-competitive as it moves toward mass production of 2-nanometer semiconductors.
Rapidus to match TSMC wafer pricing
Koike told attendees Rapidus will price its 2-nanometer chips “at the same level as, or a little lower than” those already mass-produced by TSMC. He cited expected TSMC wafer prices of roughly ¥3 million to ¥3.5 million as the reference point for Rapidus’ own pricing. The comment signals Rapidus intends to enter the market without establishing a premium price for its early-generation product.
Acknowledgment of TSMC’s market dominance
The Rapidus president acknowledged TSMC’s dominant position in the 2-nanometer segment and said the Japanese firm cannot set prices unilaterally. Koike noted the company will use TSMC’s pricing as a practical benchmark when finalizing its commercial offer. That stance reflects industry realities where a leading foundry’s price setting influences global wafer markets.
Emphasis on cost competitiveness and production speed
Koike emphasized that Rapidus must compete on both price and production throughput to secure customers. “We cannot afford to lose in the price competition,” he said, underscoring the need to control manufacturing costs as well as ramp-up velocity. The company plans to align operational efficiency and yield performance to make its 2-nanometer product attractive to chip designers.
Roadmap toward 1.4-nanometer and 1-nanometer technologies
Rapidus confirmed that development of 1.4-nanometer and 1-nanometer processes will follow once 2-nanometer mass production is achieved. The company described the 2-nanometer stage as a necessary stepping stone before committing resources to next-generation process nodes. That phased approach mirrors global semiconductor roadmaps in which commercial production is followed by iterative node shrink efforts.
Research focus on optical and quantum integration
Beyond traditional scaling, Rapidus said it is considering semiconductors that incorporate optical and quantum technologies as part of future roadmaps. Koike suggested that innovation in these areas will be pursued in parallel with node miniaturization to maintain technological differentiation. The integration of photonics or quantum-ready architectures could broaden applications and attract advanced-system customers.
Potential impact on Japan’s semiconductor strategy
Rapidus’ pricing and technological roadmap carry implications for Japan’s broader push to reestablish domestic high-end chip manufacturing. By signalling competitive wafer pricing and an explicit path to sub-2nm nodes, the company aims to reassure potential clients and policymakers about its commercial viability. Success in matching global price points while advancing next-generation research would bolster Japan’s position in an industry long dominated by overseas foundries.
Rapidus’ announcement frames the company’s immediate goal as achieving viable mass production of 2-nanometer chips at competitive cost, while laying groundwork for more advanced nodes and novel technology integration. The coming months will test Rapidus’ ability to translate those targets into manufacturing yields, customer contracts, and a sustainable role in the global semiconductor supply chain.
